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ICs for Consumer Electronics
VPS-Decoder SDA 5642-6/X
Data Sheet 02.97
SDA 5642-6/X Revision History: Previous Version: Page Page (in previous (in current Version) Version)
Current Version: 02.97
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Edition 02.97 This edition was realized using the software system FrameMaker(R). Published by Siemens AG, Bereich Halbleiter, MarketingKommunikation, Balanstrae 73, 81541 Munchen (c) Siemens AG 1997. All Rights Reserved. Attention please! As far as patents or other rights of third parties are concerned, liability is only assumed for components, not for applications, processes and circuits implemented within components or assemblies. The information describes the type of component and shall not be considered as assured characteristics. Terms of delivery and rights to change design reserved. For questions on technology, delivery and prices please contact the Semiconductor Group Offices in Germany or the Siemens Companies and Representatives worldwide (see address list). Due to technical requirements components may contain dangerous substances. For information on the types in question please contact your nearest Siemens Office, Semiconductor Group. Siemens AG is an approved CECC manufacturer. Packing Please use the recycling operators known to you. We can also help you - get in touch with your nearest sales office. By agreement we will take packing material back, if it is sorted. You must bear the costs of transport. For packing material that is returned to us unsorted or which we are not obliged to accept, we shall have to invoice you for any costs incurred. Components used in life-support devices or systems must be expressly authorized for such purpose! Critical components1 of the Semiconductor Group of Siemens AG, may only be used in life-support devices or systems2 with the express written approval of the Semiconductor Group of Siemens AG. 1 A critical component is a component used in a life-support device or system whose failure can reasonably be expected to cause the failure of that life-support device or system, or to affect its safety or effectiveness of that device or system. 2 Life support devices or systems are intended (a) to be implanted in the human body, or (b) to support and/or maintain and sustain human life. If they fail, it is reasonable to assume that the health of the user may be endangered.
SDA 5642-6/X
Table of Contents 1 1.1 1.2 1.3 1.4 2 2.1 2.2 2.2.1 2.2.2 2.2.3 2.2.4 2.3 2.4 3 4 5 5.1 5.2 5.3 5.4 5.5 5.6 6
Page 4 4 5 6 7
General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Pin Configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
System Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 I2C Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 General Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Chip Address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Write Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Read Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Order of Data Output on the I2C Bus and Bit Allocation . . . . . . . . . . . . . . . 12 Description of DAVN and EHB Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 VPS-Receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Appendix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Control Register Write (I2C-Bus Write) . . . . . . . . . . . . . . . . . . . . . . . . . . . . Data Register Read (I2C-Bus Read) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DAVN and EHB Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Position of VPS Data Lines within the Vertical Blanking Interval . . . . . . . . . Definition of Voltage Levels for VPS Data Line . . . . . . . . . . . . . . . . . . . . . . Data Format of Programme Delivery Data in the Dedicated TV Line (VPS) 20 20 21 22 23 23 24
Package Outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Purchase of Siemens I2C components conveys the license under the Philips I2C patent to use the components in the I2C system provided the system conforms to the I2C specifications defined by Philips.
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VPS-Decoder
SDA 5642-6/X
MOS 1 General Description
The SDA 5642-6 VPS decoder chip receives all VPS data. 1.1 Features
* On chip data slicer * Low external component count * I2C-Bus interface communication with external microcontroller * 5 V supply voltage * Video input signal level: 0.7 Vpp to 2.0 Vpp * Technology: CMOS * P-DIP-14-1 and P-DSO-20-1 package
P-DIP-14-1
P-DSO-20-1
Type SDA 5642-6 SDA 5642-6X
Semiconductor Group
Ordering Code Q67100-H5182 Q67106-H5183
4
Package P-DIP-14-1 P-DSO-20-1 (SMD)
02.97
SDA 5642-6/X
1.2
Pin Configurations
P-DIP-14-1
P-DSO-20-1
Figure 1
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1.3
Pin Description Pin No. Symbol Function
P-DIP-14-1 P-DSO-20-1
1 1 2 2 3 4 4 5 6
VSS VSSA VSSD
SCL SDA CS0
Ground (0 V) Analog ground (0 V) Digital ground (0 V) Not connected Serial clock input of I2C Bus. Serial data input of I2C Bus. Chip select input determining the I2C-Bus addresses: 20H / 21H, when pulled low 22H / 23H, when pulled high. Video Composite Sync output from sync slicer used for PLL based clock generation. Data available output active low, when VPS data is received. Output signaling the presence of the first field active high. Test input; activates test mode when pulled high. Connect to ground for operating mode. Phase detector/charge pump output of data PLL (DAPLL). Connector of the loop filter for the SYSPLL. Input to the voltage controlled oscillator #1 of the DAPLL. Reference current input for the on-chip analog circuit. Composite video signal input. Positive supply voltage (+ 5 V nom.). Positive supply voltage for the digital circuits (+ 5 V nom.). Positive supply voltage for the analog circuits (+ 5 V nom.).
3, 8, 13, 18 N.C.
5 6 7 8 9 10 11 12 13 14
7 9 10 11 12 14 15 16 17 19 20
VCS DAVN EHB TI PD1 PD2/ VCO2 VCO1
IREF
CVBS
VDD VDDD VDDA
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1.4
Block Diagram
Figure 2
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2 2.1
System Description Functions
Referring to the functional block diagram of the VPS decoder, the composite video signal with negative going sync pulses is coupled to the pin CVBS through a capacitor which is used for clamping the bottom of the sync pulses to an internally fixed level. The signal is passed on to the slicer, an analogue circuitry separating the sync and the data parts of the CVBS signal, thus yielding the digital composite sync signal VCS and a digital data signal for further processing by comparing those signals to internally generated slicing levels. The output of the sync separator is forwarded, on one hand, to the output pin VCS, and on the other hand, to the clock generator and the timing block. The VCS signal represents a key signal that is used for deriving a system clock signal by means of a PLL and all other timing signal. The data slicer separates the data signal from the CVBS signal by comparing the video voltage to an internally generated slicing level which is found by averaging the data signal during TV line no. 16. The clock generator delivers the system clock needed for the basic timing as well as for the regeneraton of the dataclock. It is based on two phase locked loops (PLL's) all parts of which are integrated on chip with the exception of the loop filter components. Each of the PLL's is composed of a voltage controlled relaxation oscillator (VCO), a phase/ frequency detector (PFD), and a charge pump which converts the digital output signals of the PFD to an analogue current. That current is transformed to a control voltage for the VCO by the off-chip loop filter. The generated VCO frequency is 10 MHz. All signals necessary for the control of sync and data slicing as well as for the data acquisition are generated by the Timing block. The extracted data bits of TV line no. 16 are checked for biphase errors. With no biphase errors encountered, the acquired bytes are stored in the transfer register to the I2C Bus. That transfer is signalled by a H/L transition of the DAVN output. Data are updated when a new data line has been received, provided that the chip is not accessed via the I2C Bus at the same time. A micro controller can read the stored bytes via the I2C-Bus interface at any time. However, one must be aware that the storage of new data from the acquisition interface is inhibited as long as the VPS decoder is being accessed via the I2C Bus.
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2.2 2.2.1
I2C Bus General Information
The I2C-Bus interface implemented on the VPS decoder is a slave transmitter/receiver, i.e., both reading from and writing to the VPS decoder is possible. The clock line SCL is controlled only by the bus master usually being a micro controller, whereas the SDA line is controlled either by the master or by the slave. A data transfer can only be initiated by the bus master when the bus is free, i.e., both SDA and SCL lines are in a high state. As a general rule for the I2C Bus, the SDA line changes state only when the SCL line is low. The only exception to that rule are the Start Condition and the Stop Condition. Further Details are given below. The following abbreviations are used: START: AS: AM: NAM: STOP: 2.2.2 Start Condition generated by master Acknowledge by slave Acknowledge by master No Acknowledge by master Stop condition generated by master Chip Address
There are two pairs of chip addresses, which are selected by the CS0-input pin according to the following table: CS0 Input Low High Write Mode 20 (hex) 22 (hex) Read Mode 21 (hex) 23 (hex)
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2.2.3
Write Mode
For writing to the VPS decoder, the following format has to be used: Start Step1: Step 2: Step 3: Step 4: Step 5: Step 6: Chipaddress and Write Mode AS Byte to set Control Register AS Stop
Description of Data Transfer (Write Mode) In order to start a data transfer the master generates a Start Condition on the bus by pulling the SDA line low while the SCL line is held high. The bus master puts the chip address on the SDA line during the next eight SCL pulses. The master releases the SDA line during the ninth clock pulse. Thus the slave can generate an acknowledge (AS) by pulling the SDA line to a low level. The controller transmits the data byte to set the Control register The slave acknowledges the reception of the byte. The master concludes the data communication by generating a Stop Condition.
The write mode is used to set the I2C-Bus control register which determines the operating mode: Control Register: Bit Number: 7 T7 6 T6 5 T5 4 T4 3 T3 2 T2 1 T1 0 T0
Default: All bits are set to 0 on power-up. The bits T4 through T7 are used for test purposes and must not be changed for normal operation by user software! (0 = normal operation) You may write 00H, 01H, 02H, 03H, 04H, 05H, 06H, 07H, 08H, 09H, 0AH, 0BH, 0CH, 0DH, 0EH, 0FH to the register without efect. This enables the SDA 5642-6 to be used for VPS decoding instead of the SDA 5050 or SDA 5649 without software problems.
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2.2.4
Read Mode
For reading from the VPS decoder, the following format has to be used Start : The contents of up to 16 registers (bytes) can be read starting with byte 1 bit 7 (refer to the table Order of Data Output on the I2C Bus and...) depending on the selected operating mode. Description of Data Transfer (Read Mode) Step1: To start a data transfer the master generates a Start Condition on the bus by pulling the SDA line low while the SCL line is held high. The byte address counter in the decoder is reset and points to the first byte to be output. The bus master puts the chip address on the SDA line during the next eight SCL pulses. The master releases the SDA line during the ninth clock pulse. Thus the slave can generate an acknowledge (AS) by pulling the SDA line to a low level. At this moment, the slave switches to transmitting mode. During the next eight clock pulses the slave puts the addressed data byte onto the SDA line. The reception of the byte is acknowledged by the master device which, in turn, pulls down the SDA line during the next SCL clock pulse. By acknowledging a byte, the master prompts the slave to increment its internal address counter and to provide the output of the next data byte. Steps no. 4 and no. 5 are repeated, until the desired amount of bytes have been read. The last byte is output by the slave since it will not be acknowledged by the master. To conclude the read operation, the master doesn't acknowledge the last byte to be received. A No Acknowledge by the master (NAM) causes the slave to switch from transmitting to receiving mode. Note that the master can prematurely cease any reading operation by not acknowledging a byte. The master gains control over the SDA line and concludes the data transfer by generating a Stop Condition on the bus, i. e., by producing a low/high transition on the SDA line while the SCL line is in a high state. With the SDA and the SCL lines being both in a high state, the I2C Bus is free and ready for another data transfer to be started. Chipaddress Read Mode AS 1st Byte AM ..... Last Byte NAM Stop
Step 2: Step 3:
Step 4: Step 5:
Step 6: Step 7: Step 8:
Step 9:
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2.3
Order of Data Output on the I2C Bus and Bit Allocation I2C Bus VPS Mode bit 7 6 5 4 3 2 1 0 bit 7 6 5 4 3 2 1 0 bit 7 6 5 4 3 2 1 0 bit 7 6 5 4 3 2 1 0 byte 11 bit 01) 1 2 3 4 5 6 7 bit 0 1 2 3 4 5 6 7 bit 0 1 2 3 4 5 6 7 bit 0 1 2 3 4 5 6 7
t
Byte 1
Byte 2
byte 12
Byte 3
byte 13
Byte 4
byte 14
1) Transmission bit number
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2.3
Order of Data Output on the I2C Bus and Bit Allocation (cont'd) I2C Bus Byte 5 bit 7 6 5 4 3 2 1 0 bit 7 6 5 4 3 2 1 0 bit 7 6 5 4 3 2 1 0 VPS Mode byte 5 bit 0 1 2 3 4 5 6 7 bit 0 1 2 3 4 5 6 7
Byte 6
byte 15
Byte 7
- set to "1" - set to "1" - set to "1" - set to "1" - set to "1" - set to "1" - set to "1" - set to "1"
1) Transmission bit number
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SDA 5642-6/X
2.4 DAVN EHB
Description of DAVN and EHB Outputs (Data Valid active low) (First Field active high) VPS Mode
Signal Output DAVN H/L-transition (set low) L/H-transition (set high) always set high
in line 16 when valid VPS data is received at the start of line 16 on power-up or during I2C-Bus accesses when the bus master doesn't acknowledge in order to generate the stop condition
EHB L/H-transition H/L-transition at the beginning of the first field at the beginning of the second field
In test mode (i.e. TI = high), both DAVN and EHB are controlled by the CS0 pin and reproduce the state of the CS0 input.
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3
Electrical Characteristics
Absolute Maximum Ratings TA = 25 C Parameter Ambient temperature Storage temperature Total power dissipation Power dissipation per output Input voltage Supply voltage Thermal resistance Symbol min. Limit Values typ. max. 70 125 300 10 - 0.3 - 0.3 6 6 80 0 - 40 Unit Test Condition C C mW mW V V K/W in operation by storage
TA Tstg Ptot PDQ VIM VDD Rth SU
Note: Maximum ratings are absolute ratings; exceeding any one of these values may cause irreversible damage to the integrated circuit. Operating Range Supply voltage Supply current Ambient temperature range
VDD IDD TA
4.5 0
5 5
5.5 15 70
V mA C
Note: In the operating range the functions given in the circuit description are fulfilled.
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Electrical Characteristics TA = 25 C Parameter Symbol min. Input Signals SDA, SCL, CS0 H-input voltage L-input voltage Input capacitance Input current Input Signal TI H-input voltage L-input voltage Input capacitance Input current Limit Values typ. max. Unit Test Condition
VIH VIL CI IIM
0.7 x VDD 0
VDD
10 10
V pF A
0.3 x VDD V
VIH VIL CI IIM
0.9 x VDD 0
VDD
10 10
V pF A
0.1 x VDD V
Input Signals CVBS (pos. Video, neg. Sync) Video input signal level Synchron signal amplitude Data amplitude Coupling capacitor
VCVBS
0.7
1.0
2.0
V
2 Vpp with 0.8 V VSYNC and 1.2 V VDAT 1.0 V only related to VCS signal generation
VSYNC
0.15
0.3
0.8 (1.0)
V
VDAT
0.25 0.5 1.5 x VSYNC 33
1.2
V nF
CC H-input current IIH L-input current IIL Source impedance RS Leakage resistance RC
at coupling capacitor
10 - 1000 0.91 - 400 - 100 250 1 1.2
A A M
VI = 5 V VI = 0 V
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Electrical Characteristics (cont'd) TA = 25 C Parameter Symbol min. Output Signals DAVN, EHB, VCS H-output voltage L-output voltage Limit Values typ. max. Unit Test Condition
VQH VQL
VDD - 0.5
0.4
V V
IQ = - 100 A IQ = 1.6 mA
Output Signals SDA (Open-Drain-Stage) L-output voltage Permissible output voltage
VQL
0.4 5.5
V V
IQ = 3.0 mA
PLL-Loop Filter Components (see application circuit) Resistance at PD2/ R1 VCO2 Resistance at VCO1 R2 Attenuation resistance 6.8 1200 6.8 1200 2.2 33 k k k k nF nF
R3
Resistance at PD2/ R5 VCO2 Integration capacitor C1 Integration capacitor C3 VCO - Frequence Range Adjustment Resistance at IREF R4 (for bias current adjustment)
100
k
Note: The listed characteristics are ensured over the operating range of the integrated circuit. Typical characteristics specify mean values expected over the production spread. If not otherwise specified, typical characteristics apply at TA = 25 C and the given supply voltage.
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Figure 3 I2C-Bus Timing Parameter Clock frequency Inactive time prior to new transmission start-up Hold time during start condition Low-period of clock High-period of clock Set-up time for data Rise time for SDA and SCL signal Fall time for SDA and SCL signal Set-up time for SCL clock during stop condition All values referred to VIH and VIL levels. Symbol Limit Values min. max. 100 kHz s s s s ns 1 300 4.7 s ns s 0 4.7 4.0 4.7 4.0 250 Unit
fSCL tBUF tHD; STA tLOW tHIGH tSU;DAT tTLH tTHL tSU; STO
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4
VPS-Receiver
Figure 4
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5 5.1
Appendix Control Register Write (I2C-Bus Write)
Figure 5
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5.2
Data Register Read (I2C-Bus Read)
Figure 6
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5.3
DAVN and EHB Timing
Figure 7
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5.4
Position of VPS Data Lines within the Vertical Blanking Interval
Figure 8
1) (shown for first field)
5.5
Definition of Voltage Levels for VPS Data Line
Figure 9
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5.6
Data Format of Programme Delivery Data in the Dedicated TV Line (VPS)
Figure 10
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Figure 11
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6
Package Outlines P-DIP-14-1 (Plastic Dual In-line Package)
Sorts of Packing Package outlines for tubes, trays etc. are contained in our Data Book "Package Information". Dimensions in mm Semiconductor Group 26 02.97
GPD05005
SDA 5642-6/X
P-DSO-20-1 (Plastic Dual Small Outline Package)
Sorts of Packing Package outlines for tubes, trays etc. are contained in our Data Book "Package Information". SMD = Surface Mounted Device Semiconductor Group 27
Dimensions in mm 02.97
GPS05094

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